A programmable logic device (PLD) is a standard product which can be purchased by systems manufacturers in a "blank" state and, thereafter, custom-configured into a virtually unlimited number of specific logic functions by programming the device. Because programmable logic devices provide great flexibility, these devices can be incorporated into a variety of systems.
The performance at which any such system can be operated is a function, at least in part, of the set-up time (T.sub.SU) and clock-to-output delay time (T.sub.CO) of the clock signals supplied to programmable logic device. The set-up time is the amount of time that information or data must be present at an input terminal before it can be latched and stored in the input registers of the programmable logic device. The clock-to-output delay time is the time that it takes for data to be present at an output terminal after a clock occurs. The operating frequency for the device is limited by the reciprocal of the sum of the set-up time and the clock-to-output delay time. This relationship is set out in the following equation: EQU .function..sub.OP.ltoreq.1/(T.sub.SU +T.sub.CO)
where, .function..sub.OP is the operating frequency. Consequently, in order to maximize the operating frequency for the system, and hence, its performance, both the set-up time and the clock-to-output delay time should be minimized.
With previously developed techniques, however, the set-up time for a programmable logic device can not be decreased without producing a corresponding increase in the clock-to-output delay time. This is due to the fact that in a previously developed programmable logic device, a single global clock is used to drive both input and output signals at all locations of the device. A clock distribution structure comprising various lines, buffers, and other circuitry distributes the global clock so that it can be presented substantially simultaneously to all parts of the logic device. With this distribution, a delay in the global clock is created. This delay affects both the set-up time and the clock-to-output delay time. In particular, the set-up time can be decreased if the delay is longer. However, a longer delay in the global clock causes the clock-to-output delay time to be increased. Accordingly, any improvement in performance that would otherwise be provided by a decrease in set-up time is offset by a corresponding increase in clock-to-output delay time.